Japanese Laid-Open Patent Publication No. 2003-318398 discloses an exemplary method of manufacturing a field effect transistor. In that transistor, an N−-type polycrystal silicon region is formed and adjoined to a main surface of a semiconductor substrate, wherein an epitaxial region of an N− type silicon carbide is formed on an N+-type silicon carbide substrate. The epitaxial region and the N−-type polycrystal silicon region collectively form a heterojunction. Further, a gate electrode is formed adjacent to a junction portion of the epitaxial region and the N−-type polycrystal silicon region using a gate insulating film.
The N−-type polycrystal silicon region is connected to a source electrode. Further, a drain electrode is formed at an underside of the N+-type silicon carbide substrate.
Such a semiconductor device functions as a switch of a field effect transistor by controlling an electrical potential of the gate electrode when the source electrode is grounded to apply a predetermined positive electrical potential to the drain electrode. That is, when the gate electrode is grounded, a reverse bias is applied to the heterojunction of the N−-type polycrystal silicon region and the epitaxial region such that the current does not flow between the drain and source electrodes. However, when a predetermined positive voltage is applied to the gate electrode, a gate electrical field affects the heterojunction interface of the N−-type polycrystal silicon region and the epitaxial region. Further, the thickness of an energy barrier formed by the heterojunction surface of the gate oxide film interface becomes thinner. As such, the current flows between the drain electrode and the source electrode.
In addition, the above semiconductor device uses the heterojunction portion as a control channel for blocking and conducting the current. Also, the length of the channel depends on the thickness of a hetero barrier, thereby obtaining a low resistance conduction characteristic. As such, a lower resistance conduction can be obtained as the intensity of the gate electrical field becomes greater in the heterojunction interface of the N−-type polycrystal silicon region and the epitaxial region where the gate electrode is adjoined using the gate insulating film.